通用串行总线2.0规范 英文翻译

Universal Serial Bus Specification Revision 2.0
Introduction 1.1 Motivation The original motivation for the Universal Serial Bus (USB) came from three interrelated considerations: ? Connection of the PC to the telephone It is well understood that the merge of computing and communication will be the basis for the next generation of productivity applications. The movement of machine-oriented and human-oriented data types from one location or environment to another depends on ubiquitous and cheap connectivity. Unfortunately, the computing and communication industries have evolved independently. The USB provides a ubiquitous link that can be used across a wide range of PC-to-telephone interconnects. ? Ease-of-use The lack of flexibility in reconfiguring the PC has been acknowledged as the Achilles’ heel to its further deployment. The combination of user-friendly graphical interfaces and the hardware and software mechanisms associated with new-generation bus architectures have made computers less confrontational and easier to reconfigure. However, from the end user’s point of view, the PC’s I/O interfaces, such as serial/parallel ports, keyboard/mouse/joystick interfaces, etc., do not have the attributes of plug-and-play. ? Port expansion The addition of external peripherals continues to be constrained by port availability. The lack of a bidirectional, low-cost, low-to-mid speed peripheral bus has held back the creative proliferation of peripherals such as telephone/fax/modem adapters, answering machines, scanners, PDA’s, keyboards, mice, etc. Existing interconnects are optimized for one or two point products. As each new function or capability is added to the PC, a new interface has been defined to address this need. The more recent motivation for USB 2.0 stems from the fact that PCs have increasingly higher performance and are capable of processing vast amounts of data. At the same time, PC peripherals have added more performance and functionality. User applications such as digital imaging demand a high performance connection between the PC and these increasingly sophisticated peripherals. USB 2.0 addresses this need by adding a third transfer rate of 480 Mb/s to the 12 Mb/s and 1.5 Mb/s originally defined for USB. USB 2.0 is a natural evolution of USB, delivering the desired bandwidth increase while preserving the original motivations for USB and maintaining full compatibility with existing peripherals. Thus, USB continues to be the answer to connectivity for the PC architecture. It is a fast, bi-directional, isochronous, low-cost, dynamically attachable serial interface that is consistent with the requirements of the PC platform of today and tomorrow. 1.2 Objective of the Specification This document defines an industry-standard USB. The specification describes the bus attributes, the protocol definition, types of transactions, bus management, and the programming interface required to design and build systems and peripherals that are compliant with this standard. The goal is to enable such devices from different vendors to interoperate in an open architecture.

The specification is intended as an enhancement to the PC architecture, spanning portable, business desktop, and home environments. It is intended that the specification allow system OEMs and peripheral developers adequate room for product versatility and market differentiation without the burden of carrying obsolete interfaces or losing compatibility. 1.3 Scope of the Document The specification is primarily targeted to peripheral developers and system OEMs, but provides valuable information for platform operating system/ BIOS/ device driver, adapter IHVs/ISVs, and platform/adapter controller vendors. This specification can be used for developing new products and associated software. 1.4 USB Product Compliance Adopters of the USB 2.0 specification have signed the USB 2.0 Adopters Agreement, which provides them access to a reciprocal royalty-free license from the Promoters and other Adopters to certain intellectual property contained in products that are compliant with the USB 2.0 specification. Adopters can demonstrate compliance with the specification through the testing program as defined by the USB Implementers Forum. Products that demonstrate compliance with the specification will be granted certain rights to use the USB Implementers Forum logo as defined in the logo license. 1.5 Document Organization Chapters 1 through 5 provide an overview for all readers, while Chapters 6 through 11 contain detailed technical information defining the USB. ? Peripheral implementers should particularly read Chapters 5 through 11. ? USB Host Controller implementers should particularly read Chapters 5 through 8, 10, and 11. ? USB device driver implementers should particularly read Chapters 5, 9, and 10. This document is complemented and referenced by the Universal Serial Bus Device Class Specifications. Device class specifications exist for a wide variety of devices. Please contact the USB Implementers Forum for further details. Readers are also requested to contact operating system vendors for operating system bindings specific to the USB. Background This chapter presents a brief description of the background of the Universal Serial Bus (USB), including design goals, features of the bus, and existing technologies. 2.1 Goals for the Universal Serial Bus The USB is specified to be an industry-standard extension to the PC architecture with a focus on PC peripherals that enable consumer and business applications. The following criteria were applied in defining the architecture for the USB: ? Ease-of-use for PC peripheral expansion ? Low-cost solution that supports transfer rates up to 480 Mb/s ? Full support for real-time data for voice, audio, and video ? Protocol flexibility for mixed-mode isochronous data transfers and asynchronous messaging ? Integration in commodity device technology

? Comprehension of various PC configurations and form factors ? Provision of a standard interface capable of quick diffusion into product ? Enabling new classes of devices that augment the PC’s capability ? Full backward compatibility of USB 2.0 for devices built to previous versions of the specification 2.2 Taxonomy of Application Space Figure 2-1 describes a taxonomy for the range of data traffic workloads that can be serviced over a USB. As can be seen, a 480 Mb/s bus comprehends the high-speed, full-speed, and low-speed data ranges. Typically, high-speed and full-speed data types may be isochronous, while low-speed data comes from interactive devices. The USB is primarily a PC bus but can be readily applied to other host-centric computing devices. The software architecture allows for future extension of the USB by providing support for multiple USB Host Controllers.

Figure 2-1. Application Space Taxonomy 2.3 Feature List The USB Specification provides a selection of attributes that can achieve multiple price/performance integration points and can enable functions that allow differentiation at the

system and component level. Features are categorized by the following benefits: Easy to use for end user ? Single model for cabling and connectors ? Electrical details isolated from end user (e.g., bus terminations) ? Self-identifying peripherals, automatic mapping of function to driver and configuration ? Dynamically attachable and reconfigurable peripherals Wide range of workloads and applications ? Suitable for device bandwidths ranging from a few kb/s to several hundred Mb/s ? Supports isochronous as well as asynchronous transfer types over the same set of wires ? Supports concurrent operation of many devices (multiple connections) ? Supports up to 127 physical devices ? Supports transfer of multiple data and message streams between the host and devices ? Allows compound devices (i.e., peripherals composed of many functions) ? Lower protocol overhead, resulting in high bus utilization Isochronous bandwidth ? Guaranteed bandwidth and low latencies appropriate for telephony, audio, video, etc. Flexibility ? Supports a wide range of packet sizes, which allows a range of device buffering options ? Allows a wide range of device data rates by accommodating packet buffer size and latencies ? Flow control for buffer handling is built into the protocol Robustness ? Error handling/fault recovery mechanism is built into the protocol ? Dynamic insertion and removal of devices is identified in user-perceived real-time ? Supports identification of faulty devices Synergy with PC industry ? Protocol is simple to implement and integrate ? Consistent with the PC plug-and-play architecture ? Leverages existing operating system interfaces Low-cost implementation ? Low-cost subchannel at 1.5 Mb/s ? Optimized for integration in peripheral and host hardware ? Suitable for development of low-cost peripherals ? Low-cost cables and connectors ? Uses commodity technologies Upgrade path ? Architecture upgradeable to support multiple USB Host Controllers in a system

Architectural Overview This chapter presents an overview of the Universal Serial Bus (USB) architecture and key concepts. The USB is a cable bus that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals. The attached peripherals share USB bandwidth through a hostscheduled, token-based protocol. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. Later chapters describe the various components of the USB in greater detail. 3.1 USB System Description A USB system is described by three definitional areas: ? USB interconnect ? USB devices ? USB host The USB interconnect is the manner in which USB devices are connected to and communicate with the host. This includes the following: ? Bus Topology: Connection model between USB devices and the host. ? Inter-layer Relationships: In terms of a capability stack, the USB tasks that are performed at each layer in the system. ? Data Flow Models: The manner in which data moves in the system over the USB between producers and consumers. ? USB Schedule: The USB provides a shared interconnect. Access to the interconnect is scheduled in order to support isochronous data transfers and to eliminate arbitration overhead. USB devices and the USB host are described in detail in subsequent sections. 3.1.1 Bus Topology The USB connects USB devices with the USB host. The USB physical interconnect is a tiered star topology. A hub is at the center of each star. Each wire segment is a point-to-point connection between the host and a hub or function, or a hub connected to another hub or function. Figure 3-1 illustrates the topology of the USB. Due to timing constraints allowed for hub and cable propagation times, the maximum number of tiers allowed is seven (including the root tier). Note that in seven tiers, five non-root hubs maximum can be supported in a communication path between the host and any device. A compound device (see Figure 3-1) occupies two tiers; therefore, it cannot be enabled if attached at tier level seven. Only functions can be enabled in tier seven.

Figure 3-1. Bus Topology USB Host There is only one host in any USB system. The USB interface to the host computer system is referred to as the Host Controller. The Host Controller may be implemented in a combination of hardware, firmware, or software. A root hub is integrated within the host system to provide one or more attachment points. Additional information concerning the host may be found in Section 4.9 and in Chapter 10. USB Devices USB devices are one of the following: ? Hubs, which provide additional attachment points to the USB ? Functions, which provide capabilities to the system, such as an ISDN connection, a digital joystick, or speakers USB devices present a standard USB interface in terms of the following: ? Their comprehension of the USB protocol ? Their response to standard USB operations, such as configuration and reset ? Their standard capability descriptive information Additional information concerning USB devices may be found in Section 4.8 and in Chapter 9.

3.2 Physical Interface The physical interface of the USB is described in the electrical (Chapter 7) and mechanical (Chapter 6) specifications for the bus. 3.2.1 Electrical The USB transfers signal and power over a four-wire cable, shown in Figure 3-2. The signaling occurs over two wires on each point-to-point segment. There are three data rates: ? The USB high-speed signaling bit rate is 480 Mb/s. ? The USB full-speed signaling bit rate is 12 Mb/s. ? A limited capability low-speed signaling mode is also defined at 1.5 Mb/s.

Figure 3-2. USB Cable USB 2.0 host controllers and hubs provide capabilities so that full-speed and low-speed data can be transmitted at high-speed between the host controller and the hub, but transmitted between the hub and the device at full-speed or low-speed. This capability minimizes the impact that full-speed and low-speed devices have upon the bandwidth available for high-speed devices. The low-speed mode is defined to support a limited number of low-bandwidth devices, such as mice,because more general use would degrade bus utilization. 3.2.2 Mechanical The mechanical specifications for cables and connectors are provided in Chapter 6. All devices have an upstream connection. Upstream and downstream connectors are not mechanically interchangeable, thus eliminating illegal loopback connections at hubs. The cable has four conductors: a twisted signal pair of standard gauge and a power pair in a range of permitted gauges. The connector is four-position, with shielded housing, specified robustness, and ease of attach-detach characteristics.

通用串行总线 2.0 规范 介绍 1.1 制定动机 制定通用串行总线(USB)的原始动机来自于对三个相互关联的方面的综合考虑: ? 计算机和电话之间的连接 计算机运作和通信技术的结合肯定将会成为下一代生产力应用的基础。 面向机器和人类的不 同数据从一个位置或环境到另一个位置或环境的流动取决于无处不在的便捷的连通性。 不幸 的是, 计算机工业和通信工业的发展始终是独立的。 通用串行总线提供了一个能够在大范围 的计算机到电话网络中使用的连接方式。 ? 改善使用 个人计算机在改装方面缺少的灵活性已经公认地成为其进一步发展的阿克琉斯之踵。 用户容 易掌握的图形接口和软硬件的结合以及与新一代总线结构的联系已经使得计算机的改装更 加容易。但是,末端用户则认为计算机的输入/输出接口,例如键盘、鼠标、操纵杆等设备 并没有具有即插即用的特性。 ? 端口扩展 计算机外围设备的增加一直受限于端口的可利用性。由于缺少一种双向的,低成本的,能够 满足不同速率外围设备使用的总线,一些外围设备例如电话/传真机/调制解调器的适配器, 自动应答机、扫描器、掌上电脑、键盘、鼠标等的发展都收到了阻碍。目前存在的连接仅是 针对一到两个产品的优化。 当计算机要增加一个新的功能或能力的时候, 就要定义一个新的 接口来满足这种需要。 目前通用串行总线 2.0 规范制定的动机来源于计算机性能的快速提升和对大量数据处理的 能力。与此同时,计算机外围设备也提升了性能和增加了更多的功能。在例如数字成像的用 户应用方面,需要一个高性能的连接将计算机和这些不断增加的精密的外围设备联系起来。 通用串行总线 2.0 增加了 480 兆比特/秒的传输速率来满足这种需要,而最初的通用串行总 线只有 2 兆比特/秒和 1.5 兆比特/秒两个传输速率。 通用串行总线 2.0 是在通用串行总线基 础上的伟大演变,它在提供人们渴望地高带宽的同时完美地兼容目前存在的所有外围设备。 如此一来, 通用串行总线仍将是计算机体系连通的解决答案。 通用串行总线 2.0 是一个快速 的, 双向的, 同步的, 低成本的动态连接串行接口, 能够满足计算机目前和未来的发展需要。 1.2 制定规范的目标 该文献定义了通用串行总线的工业标准。这个规范描述了总线特性、协议定义、事物类型、 总线管理、可编程接口的设计,以及建立系统和制造外围设备所要遵循的标准。 制定通用串行总线的目标是为了使不同生产商的设备能够在一个开放的体系中联系起来。 此 规范增强了商务和家用电脑现有的计算机体系。 不仅提供给系统原始设备制造商和外围设备 开发者足够的空间来满足产品的多功能性和适应不同的市场, 而且不用担心承担使用那些过 时的接口或者失去兼容性的重负。 1.3 适用范围 该规范主要面向外围设备开发者和系统设备制造商,同时给操作系统/基本输入输出系统/ 设备驱动、IHV/ISV 适配器以及控制器生产商提供很多有价值的信息。该规范可以用来开发 新产品和与之相关的软件。 1.4 通用串行总线产品兼容 通用串行总线 2.0 规范的开发者签署了通用串行总线 2.0 规范开发协议, 从投资人到开发者 对于产品中所包含的特定的关于通用串行总线 2.0 规范的知识产权提供一个互惠的专利使 用免费许可。 开发者可以通过测试由通用串行总线应用者论坛确定的项目来显示对于规范的

兼容性。 对于声明兼容此规范的产品理所当然的能够使用通用串行总线应用者论坛的法定商 标。 1.5 文献结构 第 1 章到第 5 章向所有读者提供一个综述,第 6 章到第 11 章则提供关于通用串行总线的详 细的技术资料。 ? 外围设备开发者应当着重阅读第 5 章到第 11 章 ? 通用串行总线主机控制器应用者应当着重阅读第 5 章到第 8 章,第 10 章和第 11 章 ? 通用串行总线设备驱动应用者应当着重阅读第 5 章,第 9 章和第 10 章 《Universal Serial Bus Device Class Specifications》可以作为本文献的补充和参考。各种设备 的规范是很很多种类的,可以通过通用串行总线应用者论坛来获得更多的详细资料。 读者也可以通过操作系统开发者了解通用串行总线在操作系统中的一些具体特性。

背景 本章将对通用串行总线的背景进行简要介绍,包括设计目标,总线特性和现行技术。 2.1 通用串行总线设计目标 通用串行总线是计算机体系扩展的一个工业标准, 主要适用于针对消费者和商务应用的计算 机外部设备。下面是制定通用串行总线体系的一些准则: ? 改善计算机外围设备扩展 ? 低成本将传输速率提升至 480 兆比特/秒 ? 完全支持语音、音频和视频的实时数据 ? 综合同步数据传输和异步发送 ? 整合不同设备的技术 ? 理解不同种类计算机的结构和体系特点 ? 提供一个可以快速扩展的标准接口 ? 提供可以提高计算机性能的新种类设备 ? 通用串行总线 2.0 实现对基于早期版本规范制造的设备的完全兼容 2.2 应用领域的分类 图 2-1 根据通用串行总线能够提供的数据传输速率进行分类。看以看出数据传输速率为 480 兆比特/秒的总线涵盖了高速、 中速和低速范围。 通常高速和中速范围的数据传输时同步的, 低速范围的数据传输来自于交互式设备。 通用串行总线最初设计是作为一种计算机总线而不 是易于应用到其他外围设备上的总线。 软件体系通过对多种多样的通用串行总线主机控制器 提供支持即可实现将来对通用串行总线的扩展。 2.3 特色 通用串行总线规范能够针对多样的性价比要求提供不同的选择, 以满足不同系统和元件等级 的功能区分。 其特色可以归类为以下几条: 终端用户的便于使用 ? 为电缆和连接头提供单一模型 ? 电气特性与终端用户无关 ? 自动识别外围设备,自动进行设备驱动和配置 ? 动态连接和重置外围设备 广泛的应用性 ? 适用于不同带宽的设备,传输速率从几千比特/秒到几百兆比特/秒

? 同一根电线上支持同步和异步两种数据传输模式 ? 支持对多个设备的同时操作 ? 最多支持 127 个物理设备 ? 支持在主机和设备之间传输多样的数据和信息流 ? 支持多功能的设备 ? 利用低层协议,高的总线利用率 同步带宽 ? 确定带宽和低延迟特性适合电话、音频和视频等应用 适用性 ? 支持不同大小的数据包,允许对设备缓冲器的大小进行选择 ? 通过调节数据缓冲器的大小和延迟时间来满足不同设备的数据传输速率 ? 通过协议对数据流进行缓冲处理 耐用性 ? 协议中内嵌错误处理/故障恢复机制 ? 用户感觉到设备的动态插入和移除是完全实时的 ? 支持对出错设备进行识别 与计算机产业的协作 ? 协议易于应用和整合 ? 符合计算机即插即用的体系结构 ? 改变现有的操作系统接口 低成本应用 ? 传输速率为 1.5 兆比特/秒的低成本子通道 ? 外围设备和主机硬件的最优整合 ? 促进低成本的外围设备的发展 ? 低成本的电缆和连接头 ? 运用商业技术 升级途径 ? 体系结构的可升级性支持一个系统中可以有多个通用串行总线主机控制器

体系结构综述 本章节对通用串行总线和一些关键概念进行综述。 通用串行总线是一种支持在主机计算机和 即插即用的外围设备之间进行数据交换的电缆总线。 外围设备通过主机预定的标准的协议分 享通用串行总线带宽。当主机和其它外围设备运行时,总线允许添加、配置、使用和移除外 围设备。 下面的章节将更加详细地介绍通用串行总线的不同组成部分。 3.1 通用串行总线系统描述 一个通用串行总线系统主要分为三个部分: ? 通用串行总线的互连 ? 通用串行总线的设备 ? 通用串行总线的主机 通用串行总线的互连是指通用串行总线设备与主机之间的连接和通信。 主要包括以下几个方 面: ? 总线拓扑:通用串行总线设备和主机之间的连接模型

? 内层关系:根据性能堆积,通用串行总线的任务被分配到系统的每一层 ? 数据流模式:数据在系统中通过通用串行总线在产生方和使用方之间移动的模式 ? 通用串行总线调度: 通用串行总线提供了一个共享的连接。 对连接进行了调度以支持同步 数据传输和消除仲裁的开销 通用串行总线设备和主机的详细介绍在随后的章节。 3.1.1 总线拓扑 通用串行总线将通用串行总线设备和主机连接起来。 通用串行总线的物理连接是一个层层排 列的星型拓扑结构。集线器在每一个星型的中心。每一段线段都是一个点到点的连接,从主 机连接到集线器或者功能部件, 或者集线器连接到其它集线器或功能部件。 3-1 显示了通 图 用串行总线的拓扑结构。 由于集线器和电缆的传播时间限制,允许的最大层数是七层(包括根部层) 。在第七层中, 主机和任何设备的通信路径能够最多支持五个非根集线器。 一个复合设备占有了两个层 (见 图 3-1) ,当它处以第七层时是不能被使用的。只有功能部件才能在第七层使用。 通用串行总线的主机 任何通用串行总线系统中只有一个主机。 主机计算机系统的通用串行总线接口称作主机控制 器。主机控制器可由硬件、固件或软件整合实现。根集线器集成在主机系统内部,可以提供 一个或多个连接点。 更多的关于主机的资料参见 3.9 节和第 10 章。 通用串行总线设备 通用串行总线设备如下所示: ? 集线器,向通用串行总线提供更多的连接点 ? 功能部件,为系统提供具体功能,例如综合服务数字网的连接,数字的操纵杆或扬声器 通用串行总线设备提供的通用串行总线标准接口的依据如下: ? 对通用串行总线协议的理解 ? 对标准通用串行总线操作的反馈,如配置和复位 ? 标准性能的说明资料 更多的关于通用串行总线设备的资料参见 3.8 节和第 9 章。 3.2 物理接口 通用串行总线的物理接口的电气和机械特性分别在第 7 章和第 6 章详细介绍。 3.2.1 电气特性 通用串行总线通过一种四线的电缆传输信号和电源, 如图 3-2 所示。 在每一个点到点的部分 通过两根线发送信号。 三种数据传输速率: ? 高速传输,480 兆比特/秒 ? 中速传输,12 兆比特/秒 ? 有限的低速传输模式,规定在 1.5 兆比特/秒 通用串行总线 2.0 的主机控制器和集线器提供这种能力, 能将中速和低速数据在主机控制器 和集线器之间以高速模式传输, 但在集线器和设备之间以中速或低速模式传输。 这种能力能 够将中速和低速设备占用高速设备带宽的影响最小化。 低速传输模式只能支持有限个低带宽设备, 比如鼠标, 这是因为低速模式的过多使用会降低 总线的利用率。 3.2.2 机械特性 电缆和连接头的机械特性在第 6 章中介绍。 所有的设备都具有一个上行的连接。 上行和下行 连接物理上是不可互换的,这样可以消除集线器中非法的循环连接。电缆中有四根导线:一

对标准的信号双绞线和一对标准的电源线。连接头具有四个端口,带有屏蔽外罩,并有易于 拆装的特性。